Simultaneous Multi-Threading (SMT) is a processor architecture that uses hardware multithreading to allow multiple independent threads to issue instructions during each cycle. Unlike other hardware multithreaded architectures in which only a single hardware context (i.e., thread) is active on any given cycle, SMT architecture can allow all thread contexts to simultaneously compete for and share processor resources.
An SMT processor can utilize otherwise wasted cycles to execute instructions that may reduce the effects of long latency operations in the SMT processor. Moreover, as the number of threads increases, so may the performance also increase, which may also increase the power consumed by the SMT processor.
A block diagram of a conventional SMT processor is illustrated in FIG. 1. The operation of the conventional SMT processor in FIG. 1 is discussed in Dean M. Tullsen; Susan J. Egger; Henry M. Levy; Jack L. Lo; Rebecca L. Stamm; et al., Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, The 23rd Annual International Symposium on Computer Architecture, pp. 191–202, 1996, the disclosure of which is hereby incorporated herein by reference. The architecture and operation of conventional SMT processors is well understood in the art and will not be discussed herein in further detail.